Inverter circuits for driving a load such as a motor for use in a vehicle are DC to AC converters; that is, they convert a DC voltage to an AC voltage and supply the latter to a load such as a motor. An inverter circuit for driving a motor which is inductive is composed of a MOS transistor (hereinafter abbreviated as MOS) or an insulated-gate bipolar transistor (hereinafter abbreviated as IGBT) as a switching element and a free-wheel diode (hereinafter abbreviated as FWD). The FWD bypasses and returns a current that flows through the motor while the MOS is off so that the current flowing through the motor is not varied by switching of the MOS. More specifically, when the MOS which has connected a DC power source to the motor and has applied a voltage to the motor is turned off, a current that has flown through the motor causes a reverse flow of a DC current through the FWD because of energy that is stored in the inductance L of the motor, establishing a state that is equivalent to a state that a reverse DC voltage is applied to the motor. This makes it possible to supply an AC voltage from the DC power source to the motor by switching without cutting off the motor current abruptly by switching of the MOS. To enable such an operation, the inverter circuit requires the FWD which is connected to the MOS in parallel in opposite direction. In the above inverter circuit, the MOS which functions as the switching element is required to be low in both on-resistance and switching loss. As for the FWD, the recovery characteristic and the forward loss are important characteristics.
Where a MOSFET or an IGBT which is a switching element is formed as a vertical MOS transistor having a trench gate structure (switching element), a p-type layer to serve as a channel forming region of the transistor is formed in a main-surface-side surface layer of an n-type semiconductor substrate. It is therefore possible to form a (body) diode utilizing an interface pn junction and use it as a FWD. In this structure, the vertical MOS transistor and the body diode are disposed adjacent to each other, as a result of which the semiconductor device is basically given a good switching characteristic. However, the body diode which is formed in the above manner has problems of a long recovery time and a large forward loss.
To solve the problems of the body diode which utilizes the pn-junction, the use of a Schottky barrier diode (hereinafter abbreviated as SBD) is being studied. For example, JP-A-2002-373989 (corresponding to U.S. Pat. No. 6,707,128) discloses a semiconductor device in which a vertical MOS transistor having a trench gate structure and an SBD are formed adjacent to each other on a semiconductor substrate.
FIG. 18 shows the configuration of the conventional semiconductor device disclosed in JP-A-2002-373989, that is, it is a schematic sectional view of a semiconductor device 90. FIG. 18 shows several cells of an NMOSFET (hereinafter abbreviated as MOS) transistor having a trench gate structure and an SBD which are formed on an n+/n− substrate.
In the semiconductor device 90 of FIG. 18, a p-type base layer 12 is selectively formed in a surface layer of an n− layer 11 of the n+/n− substrate in a MOS forming area 14 and an n+ source region 13 is selectively formed in a surface layer of the p-type base layer 12. Gate trenches are formed so as to extend in the depth direction from the surface of the n+ source region 13 and to reach the n− layer 11. An SBD forming area 28 is disposed so as to surround the p-type base layer 12 of the MOS forming area 14 continuously, for example. A guard ring region 17 is formed so as to surround the SBD forming area 28 by the same process as the p-type base layer 12 is formed.
An interlayer insulating film 19 is deposited on the substrate in the MOS forming area 14, and plural contact holes are formed through the interlayer insulating film 19 at prescribed positions. A barrier metal 21 is formed on the surface of the n− layer 11 in the SBD forming area 28 and the surfaces of those portions of the n+ source region 13 which correspond to the contact holes formed through the interlayer insulating film 19. The barrier metal 21 is in Schottky contact with the surface of the n− layer 11 in the SBD forming area 28 and is in ohmic contact with the surfaces (high-concentration regions) of the portions of the n+ source region 13. Furthermore, a first main electrode 1 made of a metal to serve as both of an anode electrode of the SBD and a source electrode of the MOS is formed on the barrier metal 21. A second main electrode 22 to serve as both of a cathode electrode of the SBD and a drain electrode of the MOS is formed on almost the entire chip back surface.
Configured in such a manner that the MOS and the SBD are connected to each other in parallel in opposite directions, the semiconductor device 90 of FIG. 18 can be applied to the above-described inverter circuit with the SBD used as an FWD. Having a lower threshold voltage than pn-junction diodes such as the above-described body diode, when used as the FWD, the SBD is superior in the recovery characteristic and can lower the forward loss.
On the other hand, whereas the above-described body diode is formed by utilizing the p-type layer (corresponding to the p-type base layer 12 shown in FIG. 18) to serve as the MOS channel forming area, in the semiconductor device 90 of FIG. 18 the independent SBD forming area 28 is provided so as to continuously surround the p-type base layer 12 which exists in the MOS forming area 14. Therefore, the semiconductor device 90 has problems that the switching characteristic is basically bad and the chip cost is high because of an increased chip area.
One method for suppressing the increase of the chip area of the semiconductor device 90 is to increase the intervals between the gate trenches in the MOS forming area 14 and dispose an SBD between the adjoining gate trenches. However, this configuration raises another problem that the increased intervals between the gate trenches lower the breakdown voltage of the MOS. Furthermore, in this configuration, since the MOS and the SBD are disposed in a limited area, the individual regions of the p-type base layer 12 of the MOS need to be sufficiently narrow taking lateral diffusion into consideration. However, since the p-type base layer 12 of the MOS corresponds to the bases of parasitic bipolar transistors, parasitic operations tend to occur unless the individual regions of the p-type base layer 12 are sufficiently wide. This means a problem that the L load surge resistance is low.
Thus, it is desired to provide a semiconductor device in which a vertical MOS transistor having a trench gate structure and a Schottky barrier diode are formed adjacent to each other on a single semiconductor substrate, and which is superior in the diode recovery characteristic and can lower the forward loss, is free of reduction in transistor breakdown voltage and surge resistance, is superior in the switching characteristic, and is small in size and inexpensive.
FIG. 28 is a sectional view of a conventional semiconductor device which is equipped with a vertical MOSFET having a trench gate structure. As shown in FIG. 28, an n− drift layer J2 and a p-type base layer J3 are formed on an n+ silicon substrate J1. Plural n+ source regions J4 are formed in surface portions of the base layer J3. The silicon substrate J1, the drift layer J2, the base layer J3, and the source regions J4 constitute a semiconductor substrate J5. Trenches J6 are formed in the semiconductor substrate J5 so as to penetrate through the base layer J3 and reach the drift region J2. Silicon oxide films (gate oxide films) J7 are formed so as to cover the inner wall surfaces of the trenches J6, respectively, and gate electrodes J8 are formed on the surfaces of the silicon oxide films J7 so as to be buried in the trenches J6, respectively. Trench gates are thus formed.
A BPSG film J9 is formed so as to cover the gate electrodes J8, and a source electrode J10 is formed so as to be electrically connected to the source regions J4 and the base layer J3 through contact holes that are formed through the BPSG film J9. A drain electrode J11 is formed on the back-surface side of the semiconductor substrate J5. The semiconductor device which is equipped with the MOSFET having the trench gate structure is thus constructed (refer to JP-A-2005-333112, for example).
In the MOSFET having the above structure, since the base layer J3 necessarily exists between the trenches, body diodes which are formed by the pn junctions of the p-type base layer J3 and the combination of the n-type drift layer J2 and the silicon substrate J1 are disposed between the trenches. Where the semiconductor devices having the above structure are applied to an H-bridge circuit such as a motor drive circuit and the individual MOSFETs are on/off-driven by a PWM control, a return current flows through the body diodes of the MOSFETs located on the high side, which causes a return current loss which is mainly due to Vf of the body diodes.
Thus, it ie required for a semiconductor device to reduce a return current loss which is mainly due to Vf of a body diode.